[Weekly Review] 2020/02/17-23

Published: February 23, 2020 by SingularityKChen (Last updated: March 07, 2020 )

• Categories:
• WeeklyReview 81

• Tags:
• Chisel 22
• Scala 10

• 2020/02/17-23
  • Chisel & Scala Syntax
    • Pay Attention To
    • CombLoopException: VecInit and RegInit
    • Generate Random List

2020/02/17-23

This week, I continued on the survey of ML4HPC and found several papers of Indiana University, which described the definitions of ML4HPC and its subcategories. Also, I finished the draft implementation of GLB cluster with some test.

Chisel & Scala Syntax

Pay Attention To

I made a mistake by mismatch the width of one register or IO, so the results can be wrong. And it took me a long and hard time to find this. I think I'd better assign the values explicit.

CombLoopException: VecInit and RegInit

firrtl.transforms.CheckCombLoops$CombLoopException: : [module GLBCluster] Combinational loop detected:
GLBCluster.theSRAMsState_1
GLBCluster._T_60	 @[Conditional.scala 37:30]
GLBCluster._GEN_7	 @[Conditional.scala 40:58]
GLBCluster.theSRAMsState_1	 @[GLBCluster.scala 21:38 GLBCluster.scala 42:20 GLBCluster.scala 47:20]
firrtl.transforms.CheckCombLoops$CombLoopException: : [module GLBCluster] Combinational loop detected:
GLBCluster.theSRAMsState_0
GLBCluster._T_30	 @[Conditional.scala 37:30]
GLBCluster._GEN_3	 @[Conditional.scala 40:58]
GLBCluster.theSRAMsState_0	 @[GLBCluster.scala 21:38 GLBCluster.scala 42:20 GLBCluster.scala 47:20]
firrtl.passes.PassException: 2 errors detected!
firrtl.passes.PassExceptions: 
firrtl.transforms.CheckCombLoops$CombLoopException: : [module GLBCluster] Combinational loop detected:
GLBCluster.theSRAMsState_1
GLBCluster._T_60	 @[Conditional.scala 37:30]
GLBCluster._GEN_7	 @[Conditional.scala 40:58]
GLBCluster.theSRAMsState_1	 @[GLBCluster.scala 21:38 GLBCluster.scala 42:20 GLBCluster.scala 47:20]
firrtl.transforms.CheckCombLoops$CombLoopException: : [module GLBCluster] Combinational loop detected:
GLBCluster.theSRAMsState_0
GLBCluster._T_30	 @[Conditional.scala 37:30]
GLBCluster._GEN_3	 @[Conditional.scala 40:58]
GLBCluster.theSRAMsState_0	 @[GLBCluster.scala 21:38 GLBCluster.scala 42:20 GLBCluster.scala 47:20]
firrtl.passes.PassException: 2 errors detected!

Source code:

private val theSRAMsState = VecInit(Seq.fill(2){RegInit(oneSRAMIdle)})

We need to change the order of Reg and Vec.

private val theSRAMsState = RegInit(VecInit(Seq.fill(2){oneSRAMIdle}))

Generate Random List

  def RandomDataGen(n:Int, dataWidth: Int): List[Int] = {
    var resultList: List[Int] = Nil
    while ( resultList.length < n ){
      val randomNum = (new Random).nextInt(pow(2, dataWidth).toInt)
      resultList = resultList:::List(randomNum)
      /*
      if( !resultList.exists( s=>s==randomNum )){
        resultList = resultList:::List(randomNum)
      }
      */
    }
    resultList
  }