[Weekly Review] 2020/08/03-09

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2020/08/03-09

This week, I still worked on the Loosely Timed TLM.

I do realize that either Chisel or Verilog is used to implement the design, while I need some rapid tools to verify my design's function and a coarse-grained performance results.

Chisel is a wonderful implementation tool under developed. I think I'll use it after the modelling in SystemC or Python(if any) as a academic implementation codes.

As for the modelling, I found that currently, I just simply write the pure C++ code as small compute units while only use SystemC for the communications between the second-level top unit and memories.

But I think I can change those pure C++ function calls to SystemC control signals after the functional verification.

I posed two posts this week.