[Workshop] Hot Chips 2020 Marvell Details ThunderX3 CPUs

Published: September 04, 2020 by SingularityKChen (Last updated: September 04, 2020 )

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• Hot Chips 2020 Marvell Details ThunderX3 CPUs

Hot Chips 2020 Marvell Details ThunderX3 CPUs¹

Marvell here opted to evolve its own interconnect microarchitecture which has now evolved from a simple ring design, to a switched ring with three sub-rings, or columns. Ring stops consist of CPU tiles with 4 cores and two L3-slices with 3MB of cache. This gives a full die with 15 ring stops (3x5 columns) and the full 60 cores 90MB of total L3 cache which is a quite respectable amount.

1. Anandtech. https://www.anandtech.com/show/15995/hot-chips-2020-marvell-details-thunderx3 ↩