[Weekly Review] 2021/02/15-2021/02/21
2021/02/15-2021/02/21
Last week, I was working on the two projects parallelly, usually after I modified the Pulpissimo C++ testbench file and execute the simulation, I would work on another project and modify the hardware Python model.
After I fixed the C++ testbench, I found that there are some logic bugs in the hardware caused by our new added hardware converter. When the submodule require data from our hardware, our hardware forward those requires directly to the bus instead of processing those requires and then sending requires to the bus.
I think I still need to think things more thoroughly to avoid this kind of problem. I need to be forethoughtful and considering not only the submodules but also the upper module. And the require signal, grant, data, and valid should exactly match with each other.