[Glean] Logic Synthesis, Physical Synthesis
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Logic Synthesis, Physical Synthesis
Quick Overview1
Logic synthesis creates a netlist of gates from RTL Verilog. It also includes other steps such as technology mapping where the gates are selected from a set of libraries provided and timing/area/power optimisation.
Physical synthesis transforms the gate level netlist to a layout that can be realised (etched) on silicon. It includes floor planning, placement (fixing location of the gates), routing ( wires in gate level netlist are assigned metal layers etc), clock tree synthesis and multiple different steps of local and global optimisations.
Definition of Logic Synthesis2
Logic synthesis takes as an input a description of a circuit expressed in a high-level language such as Verilog or VHDL. Other inputs include timing constraints for the design as well as the specific target implementation technology. Logic synthesis software then analyzes these inputs and maps them to a particular set of interconnected logic elements taken from cell libraries that are also provided as inputs to the process.
Objective of Logic Synthesis2
Objectives of logic synthesis include optimization of timing, area, and power of the resultant design. The output of logic synthesis was then given to a place-and-route tool that would perform the necessary steps to physically implement the circuit in silicon.
Problem of Logic Synthesis2
After placement and routing, the physical effects associated with wiring (e.g., increased signal delay and voltage drop) along with parasitic effects due to the proximity of certain devices cause the “physical” version of the circuit to behave differently than the “logical” version of the circuit. The result is many iterations between logic synthesis and place-and-route to achieve a working design.
Why Physical Synthesis2
Physical synthesis takes these implementation effects into consideration. An early floorplan of the design along with detailed routing estimates helps to provide early data on the previously mentioned physical effects. As a result, physical synthesis provides a convergent design flow that requires far fewer iterations.
The overall goal of physical synthesis is to consider late-stage implementation effects early in the design process with sufficient detail to create a convergent design flow. Early design results then fit the requirements of late-stage implementation with minimal need for re-work. The general process of considering late-stage impacts earlier is called a shift-left approach.
Some Ideas1
The logical and physical synthesis serve different targets in the RTL logic to netlist conversion.
- The constraints(SDC) are more mature in a physical synthesis. The logical synthesized netlist and floorplan are the inputs for a physical synthesis flow. So the area and placement of cells will be more accurate after physical synthesis.
- The logical synthesis optimizes the logic, timing and functionality implementation using minimum gates and DRV.
- The physical synthesis optimises the area, power, clock and power gating, scan optimisation along with constraints in logical synthesis.
- The target of physical synthesis is to achieve the minimum area usage at the required speed for a design. And for logical synthesis is timing with no functionality differences.