[Glean] Backend Design Flow: SDC and Timing Constraints

Published: April 22, 2023 by SingularityKChen (Last updated: April 03, 2023 )

• Categories:
• Glean 53

• Tags:
• Cadence 5
• Genus 4
• Innovus 2
• SDC 1

• Backend Design Flow: SDC and Timing Constraints
  • Summary
  • Adjusting Timing Constraints in SDC File
  • Clock Period and Uncertainty in Different Stages
    • Synthesis
    • Place and Route
    • Signoff (Static Timing Analysis)

The first half of this article is gleaned by me and the next half is generated by ChatGPT4.

Backend Design Flow: SDC and Timing Constraints

Summary

In the backend design flow, using a single Synopsys Design Constraints (SDC) file from synthesis to place and route (P&R) is a common approach. However, adjustments to the timing constraints might be necessary to avoid over-constraining or under-constraining the design. Clock period and uncertainty values are typically set differently at various stages in the design flow. Collaboration with the design team, foundry, and EDA tool vendors is crucial for determining appropriate values.

Adjusting Timing Constraints in SDC File

1. Clock Uncertainty: Relax clock uncertainty values if needed to account for manufacturing variability or aggressive initial values.
2. Input/Output Delay Constraints: Align the constraints with actual delays of the input and output paths of the design.
3. Multicycle Paths: Identify legitimate multicycle paths and constrain them properly to provide flexibility for optimization.
4. False Paths: Specify any false paths to reduce timing analysis complexity and make meeting constraints easier.

Clock Period and Uncertainty in Different Stages

Synthesis

• Clock Period: Set based on target performance (frequency) of the design.
• Clock Uncertainty: Set to a smaller percentage of the clock period (e.g., 2-5%) to account for synthesis tool inaccuracies and minor variations.

Place and Route

• Clock Period: Adjust if the initial value is too aggressive or if there are changes in design requirements.
• Clock Uncertainty: Set to about 5-10% of the clock period to account for on-chip variation (OCV), clock jitter, and other effects.

Signoff (Static Timing Analysis)

• Clock Period: Use the most accurate models and tools available to verify the design's timing.
• Clock Uncertainty: Refine based on actual variability observed in the design and the manufacturing process, typically 5-15% of the clock period.

Note: The percentages mentioned are general guidelines and should be adjusted based on the specific requirements of your design and the process technology.