[Glean] AXI Bus Introduction

Published: April 28, 2024 by SingularityKChen (Last updated: August 19, 2024 )

• Categories:
• Glean 53

• Tags:
• AMBA 1
• AXI 1

• AXI Bus
  • Introduction
  • VALID/READY Handshake
• Reference

AXI Bus

Introduction¹

AXI contains five channels: read address, read data, write address, write data, and write response. Each channel has its own independent protocol.

• The read address channel (AR) is used to send read requests to the slave
• The read data channel is (R) used to send read data from the slave to the master
• The write address channel (AW) is used to send write requests to the slave
• The write data channel (W) is used to send write data from the master to the slave
• The write response channel (B) is used to send write responses from the slave to the master

VALID/READY Handshake²

The AXI protocol uses a valid/ready handshake mechanism to ensure that both the master and the slave are ready to transfer data. The master asserts the valid signal to indicate that it has data to transfer, and the slave asserts the ready signal to indicate that it is ready to accept the data. The transfer of data occurs when both the valid and ready signals are asserted.

VALID 信号一旦置起就不能置低，直到完成握手（handshake occurs）,至少传输一周期数据。

The VALID signal must remain asserted until the handshake occurs, and at least one data transfer occurs.³

Reference

1. 深入 AXI4 总线（二）架构 ↩

2. 深入 AXI4 总线（一）握手机制 ↩

3. AXI总线总结 ↩